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HD151011
Dual BCD Programmable Counter with Synchronous Preset Enable
ADE-205-100(Z) Rev 0 April 1995
The HD151011 has BCD decimal two digits down counter and D-type Flip Flop. The counter can set up to max 99 counts and synchronous preset (SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider.
Features
* High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) * High output current Fanout of 10 LS TTL Loads * Wide operating voltage Vcc = 2 to 6 V * Low supply current (Ta = 25C) Icc (Static) = 4 A (max)
HD151011
Function Table
Control Inputs CLR H X -- -- L H PR H X -- -- H L SPE H L -- -- -- -- C/T X X H L -- -- Mode Generally count Synchronous preset -- -- Initialize of Q output Initialize of Q output Operation Description Down count at the rise edge of clock (CLK), Down count at the fall edge of clock (CLK) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK) Clock inputs (CLK, CLK) is CMOS level Clock inputs (CLK, CLK) is TTL level Initialize of Q = "L" Initialize of Q = "H"
H: High level L: Low level Z: Immaterial --: Irrespective of condition 1. Synchronous preset (SPE) input can set max 99 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. 4. Clock inputs (CLK, CLK) is selectable CMOS level (VCC = 2.0 to 6.0 V) and TTL level (VCC = 4.5 to 5.5V) (Jn, C/T, PR, CLR and SPE inputs are CMOS level) Note: Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB)
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HD151011
Pin Arrangement
CO 1 J0 2 J1 3 J2 4 J3 5 J4 6 J5 7 J6 8 J7 9 GND 10
20 VCC 19 (Test 1)* 18 (Test 2)* 17 C / T 16 CLK 15 CLK 14 Q 13 PR 12 SPE 11 CLR
(Top view) * Pins 18 and 19 are for function test only and should be open.
Pin Description
Pin Name Input pins J0 to J7 C/T CLK, CLK SPE PR CLR Output pins CO Q Pin Description Count data input for option Level change input for CLK, CLK (CMOS level or TTL level) Clock inputs CLK : Rise edge trigger CLK : Fall edge trigger Preset input for Jn data Preset input for D-type Flip Flop (Initialize "L" at Q output) Clear input for D-type Flip Flop (Initialize "H" at Q output) Output for BCD decimal counter Output for D-type Flip Flop
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HD151011
Absolute Maximum Ratings
Item Supply voltage Input / output voltage VCC, GND current Output current / pin Power dissipation Storage temperature Input diode current Output diode current Symbol VCC VIN / V OUT I CC, I GND I OUT PT Tstg I IK I OK Ratings -0.5 to 7.0 -0.5 to VCC +0.5 50 25 757 -65 to 150 20 20 Unit V V mA mA mW C mA mA
Notes: 1. The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 2. All voltage values except for differential input voltage are with respect to network ground terminal.
Recommended Operating Conditions
Item Supply voltage Input / output voltage Operating temperature Input rise / fall time
*1
Symbol VCC VIN / Topr VCC = 2.5 V VCC = 4.5 V VCC = 5.5 V tr, tf
OUT
Min 2 0 -40 0 0 0
Typ -- -- -- -- -- --
Max 6 VCC +85 1000 500 400
Unit V V C ns
Note:
1. This item guarantees maximum limit when one input switches.
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HD151011
Logic Diagram
C/T J0 J1 J2 J3 J4 J5 J6 J7 J0 BCD decimal counter J1 J2 J3 J4 J5 J6 J7 CLK CLK CLK CO PR PR D CO SPE CK CLR SPE CLR Q Q Q
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HD151011
Electrical Characteristics
Ta = 25C Item High level input voltage Symbol VCC VIH 2.0 4.5 6.0 2.0 4.5 6.0 4.5 to 5.5 Low level input voltage VIL 2.0 4.5 6.0 2.0 4.5 6.0 4.5 to 5.5 High level output voltage VOH 2.0 4.5 6.0 4.5 6.0 Low level output voltage VOL 2.0 4.5 6.0 4.5 6.0 Input capacitance IIN Supply current I CC 6.0 6.0 Min 1.5 3.15 4.2 1.5 3.15 4.2 2.0 -- -- -- -- -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.0 4.5 6.0 4.31 5.80 0.0 0.0 0.0 0.17 0.18 -- -- Max -- -- -- -- -- -- -- 0.5 1.35 1.8 0.5 1.35 1.8 0.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to 85C Min 1.5 3.15 4.2 1.5 3.15 4.2 2.0 -- -- -- -- -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- 0.5 1.35 1.8 0.5 1.35 1.8 0.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40.0 mA mA I OL = 4 mA I OL = 5.2 mA VIN = VCC or GND VIN = VCC or GND V VIN = VIH or VIL I OH = -4 mA I OH = -5.2 mA I OL = 20 A V VIN = VIH or VIL C/T = VIL I OH = -20 A V J0 to J7 C/T, SPE PR, CLR CLK, CLK C/T = VIH C/T = VIL Unit V Test Conditions J0 to J7 C/T, SPE PR, CLR CLK, CLK C/T = VIH
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HD151011
Switching Characteristics (CL = 50 pF, tr = tf = 6 ns)
Ta = 25C Item Maximum clock frequency Symbol VCC fmax 2.0 4.5 6.0 Output rise / fall time t TLH t THL 2.0 4.5 6.0 Propagation delay time t PLH t PHL 2.0 4.5 6.0 t PLH t PHL 2.0 4.5 6.0 t PLH t PHL 2.0 4.5 6.0 Pulse width (CLK, CLK, PR, CLR) tw 2.0 4.5 6.0 Setup time (Jn - CLK, CLK) (SPE, CLK, CLK) Hold time (Jn - CLK, CLK) (SPE, CLK, CLK) Input capacitance Power dissipation capacitance Note: CIN CPD th ts 2.0 4.5 6.0 2.0 4.5 6.0 -- -- Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 100 20 17 15 10 5 -- -- Typ -- 36 -- 30 8 7 -- 30 -- -- 35 -- -- 18 -- -- -- -- -- -- -- -- -- -- 5 48 Max 4 20 24 75 15 13 250 50 45 300 60 53 150 30 25 -- -- -- -- -- -- -- -- -- 10 -- Ta = -40 to 85C Min -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 125 25 21 15 10 5 -- -- Max 3 16 19 95 19 16 318 63 53 380 75 65 185 38 32 -- -- -- -- -- -- -- -- -- 10 -- pF pF ns ns ns PR or CLR to Q CLK or CLK to Q ns CLK or CLK to CO ns Unit MHz Test Conditions
1. CPD is equivalent capacitance inside of the IC calculated from the operating current without load (see test circuit). The average operating current without load is calculated according to the expression below. I CC (opr) = CPD V CC * fIN + ICC
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HD151011
* Test Circuit
VCC Input Pulse generator See Function Table Zout = 50 Input Pulse generator Zout = 50 VCC
J0 J1 Output Q Output J7 C/T CLK CLK SPE PR CLR CL CL CO
Note: 1. CL includes probe and jig capacitance.
* Waveforms - 1
tw 6 ns tw 6 ns 90 % 90 % *1 *1 V ref V ref 10 % t PLH 90 % 10 % t PHL 90 % 50 % 10 % t THL t PHL 90 % 90 % 50 % 10 % t THL *1
CLK
VIH
CLK
GND
VOH
Q
10 %
50 % t TLH t PLH
VOL
VOH
CO
10 %
50 % t TLH
VOL
Note:
1.
In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC x 50%
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HD151011
* Waveforms - 2
6 ns 90 % 90 % 50 % 10 % 10 % ts
VCC
Jn
GND
90 % *1 V ref
CLK
VIH
*1
CLK
10 %
10 % 6 ns
GND VOH
*2
F/F Output
Internal delay
50 %
VOL
Notes:
1. 2.
In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC x 50% F/F output is internal signal of IC.
* Waveforms - 3
6 ns 90 % 90 % 50 % 10 % th 10 %
VCC
Jn
GND VIH
*1
CLK
*1 V ref
90 %
CLK
10 %
10 % 6 ns
GND VOH
*2
F/F Output
Internal delay
50 %
VOL
Notes:
1. 2.
In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC x 50% F/F output is internal signal of IC.
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HD151011
* Waveforms - 4
6 ns 90 % 90 % 50 % 10 % 10 % ts
VCC
SPE
GND
90 % *1 V ref
CLK
VIH
*1
CLK
10 %
10 % 6 ns
GND VOH
*2
F/F Output
Internal delay
50 %
VOL
Notes:
1. 2.
In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC x 50% F/F output is internal signal of IC.
* Waveforms - 5
6 ns 90 % 90 % 50 % 10 % th 10 %
VCC
SPE
GND VIH
*1
CLK
*1 V ref
90 %
CLK
10 %
10 % 6 ns
GND VOH
*2
F/F Output
Internal delay
50 %
VOL
Notes:
1. 2.
In case of C/T = "L", CLK, CLK is V IH = 3 V, Vref is 1.3 V In case of C/T = "H", CLK, CLK is V IH = VCC, Vref is VCC x 50% F/F output is internal signal of IC.
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HD151011
* Waveforms - 6
tf 90 % tr 90 % 50 % 10 % tw tf 90 % tr 90 % 50 % 10 % tw t PHL t PLH
VCC
CLR
50 % 10 %
GND
VCC
PR
50 % 10 %
GND
VOH Q
50 % 50 %
VOL
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HD151011
Timing Chart
CLK
SPE
J0
J1
J2
J3
J4

J5 J6 J7 (CO=SPE) CLR (Initialize of CLR) Q PR (Initialize of PR) Q Count 5 4 3 2 1 0 3 2 1 0 23 22 12
HD151011
Example of Application Circuit * AC Signal Generator for STN Type Liquid Crystal Panel
CLK (CLK) : CMOS level input Initialize counter : 32
CO J0 J1 J2 J3 J4 J5 J6 J7 GND
V CC (Test 1) (Test 2) C/T CLK CLK Q PR SPE CLR * * NC NC
*When initializing output D-F/F apply "L"
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HD151011
Timing Chart * Example of AC Signal Generator
1 2 3 31 32 33 34 35 65 66 67 68
CLK
SPE J0
J1 1digit=2 J2
J3
J4

J5 2digits=3 J6 J7 (CO=SPE) CLR Q PR Q Count 32 31 30 2 1 0 32 31 1 0 32 31
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HD151011
Package Dimensions
Unit : mm
Unit: mm
6.50 6.80 Max 20 11 4.40 1 10 0.65 0.22 +0.08 -0.07 0.20 0.06 0.13 M 0.65 Max 0.17 0.05 0.15 0.04 1.10 Max 0.07 +0.03 -0.04 0 - 8 0.50 0.10 1.0 6.40 0.20 0.10
Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-20DA -- -- 0.07 g
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Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
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URL
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Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.

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